The present invention relates generally to memory circuits and particularly to memory cells capable of performing logical functions within the memory cell.
Conventional memory cells include a bi-stable latch circuit formed of cross-coupled MOS transistors. For stable operation, only one of the transistors is conducting while the other transistor is non-conducting. The cell is switched from storing a logical 1 to a logical 0 by reversing the non-conducting transistor to conducting and the conducting transistor to non-conducting in a conventional manner. The conducting path for one transistor connects from a reference (such as Vcc), along a conduction path through the transistor from drain to source to a sink such as ground. The conducting path for the complementary transistor is similarly from a reference along a conduction path through the other transistor from drain to source to a sink. The conduction path from one transistor is connected through one passing gate transistor to a write bit line, WB. Similarly, the conduction path for the same transistor is connected through another passing gate transistor to a read bit line, RB.
The complementary transistor of the latch has a complementary conduction path connected through a passing transistor to a write bit line, WB. Another passing transistor connects the complementary conduction path to a read bit line RB. The passing gates for both the write bit, WR, and write bit, WB, lines have their gates connected to a common write word line, WW. Similarly, the passing gates for the read bit, RB, line and the read bit, RB, line have their gates connected in common to a read word, RW, line.
The conventional operation of a memory cell has a coincidence of write word, WW, line and write bit, WB, line signals to write into the latch circuit to store a logical 1 and the coincidence of the write word, WW, line and the write bit, WB, line to write a logical 0 into the latch circuit. In order to read from the latch circuit, the read word, RW, line is energized and complementary signals appear on the read bit, RB, line and the read bit, RB, line.
In conventional memory cells, only one write word line and one read word line are provided. If more than one value is to be used to control a word line, either read or write, then external control logic, such as a logical AND, must be used externally to the memory cell. The external logic requires additional circuitry which requires additional area on a semiconductor chip and which causes additional delay in accessing the memory cell.
It is an object of the present invention to reduce the area required to do logical functions such as logical AND's and to increase the speed of memory cell operation.